1. Field of the Invention
The present invention generally relates to integrated circuit dynamic random access memories, and more particularly to trench capacitor construction.
2. Background Description
As dynamic random access memory (DRAM) cells are scaled to meet chip-size requirements for future generations, the channel length of transfer devices on the surface of the silicon substrate can no longer be scaled without degrading subthreshold leakage requirements (or retention time requirements). Process steps become complex and incompatible with standard DRAM processes, when vertical transfer devices in the DRAM cell are employed to decouple the channel length from layout ground rules.